1. Field of the Invention
The present invention relates to variable capacitor elements, and more particularly to variable capacitor elements contained in integrated circuits for use in high frequency circuits.
2. Description of the Related Art
With the recent developments in markets for the mobile communication devices such as cellular phones, it has become increasingly important to integrate, on ICs, elements such as inductors and capacitors that conventionally have been used as separate components, in order to realize the miniaturization, lower cost and the like for circuits. One of such elements is the variable capacitor element. Variable capacitor elements are used for applications such as changing the oscillation frequency of an oscillation circuit.
Examples of conventional technologies of this kind include a frequency synthesizer containing a VCO circuit with switching means for a capacitor (see e.g., JP2001-339301 A), a band-switched integrated voltage controlled oscillator (see e.g., JP2001-196853 A) and a voltage controlled oscillator with an additional function of frequency correction using a variable capacitor element (see e.g., JP2001-352218 A).
FIG. 6A shows the planar structure of a conventional variable capacitor element constructed on an IC. FIG. 6B shows a cross section taken along line B—B in FIG. 6A. In FIGS. 6A and 6B, a numeral 301 denotes a p-type silicon substrate; 302 denotes an n-type buried electrode layer; 303 denotes an n-type surface electrode layer; 304 and 309 denote a first gate electrode layer and a second gate electrode layer, respectively; and 305 and 310 denote a first gate oxide film and a second gate oxide film, respectively. Numerals 306 and 311 denote via-holes on the first and second gate electrodes, respectively; 307 and 312 denote wiring layers for first and second gate electrodes, respectively; 308 denotes an insulator layer; 313 denotes a via-hole on the n-type buried electrode; and 314 denotes a wiring layer for the n-type buried electrode.
The n-type buried electrode layer 302 is formed in a surface region of the p-type silicon substrate 301, which is of a different conductivity type. The first and second gate oxide films 305 and 310 each have a rectangular shape, and are formed such that the long sides of the films 305 and 310 are opposed closely to each other. The short sides of the first and second gate oxide films 305 and 310 are formed in contact with the insulator layer 308. The first and second gate electrode layers 304 and 309 are formed on the first and second gate oxide films 305 and 310 so as to extend over the insulator layer 308. The lead portions of the first and second gate electrode layers 304 and 309 are connected by the via-holes 306 and 311 to the wiring layers 307 and 312 disposed above the insulator layer 308 in a region excluding the first and second gate oxide films 305 and 310. The n-type surface electrode layer 303 is formed in a surface region of the n-type buried electrode layer 302, except for the region of the first and second gate oxide films 305 and 310. The lead portion of the n-type buried electrode layer 302 is disposed in close proximity to the outer long sides of the first and second gate oxide films 305 and 310, and connected by the via-hole 313 to the wiring layer 314 for the n-type buried electrode.
The thickness of the depletion layers of the MOS junction between the n-type buried electrode layer 302 and the first and second gate electrode layers 304 and 309 is changed by changing the respective potential difference between the n-type buried electrode layer 302 and the first and second gate electrode layers 304 and 309. Consequently, the capacitance value between the n-type buried electrode layer 302 and the first and second gate electrode layers 304 and 309 changes, and the device operates as a variable capacitor element. Additionally, the n-type buried electrode layer 302 and the silicon substrate 301 are separated by the depletion layer of a pn junction.
A similar variable capacitor element may be constructed using the MOS junction between a p-type buried electrode layer and each of the first and second gate electrode layers 304 and 309.
In the above-described structure, since the first gate electrode layer 304 and the second gate electrode layer 309 are formed such that the long sides of the layers are opposed closely to each other, the parasitic resistance due to the n-type buried electrode layer 302 can be reduced between the respective variable capacitor elements. However, since the first and second gate electrode layers 304 and 309 have an oblong rectangular shape, the distance from the via-holes 306 and 311 on the first and second gate electrodes to the respective variable capacitor elements becomes longer. Accordingly, the parasitic resistance due to the first and second gate electrode layers 304 and 309 becomes larger. Therefore, there has been the problem that the parasitic resistance between the respective variable capacitor elements increases, resulting in a greater power loss for high frequency signals. Particularly, when the above-described variable capacitor element is used in a resonance circuit of an oscillation circuit, the noise characteristics of the oscillation output deteriorates owing to the parasitic resistance between the respective variable capacitor elements.